1. Field of the Invention
This invention relates to a sample rate conversion system having an interpolation function and, more particularly, to a sample rate conversion system which can be suitably applied to a sample rate converter (SRC) for converting sample rates of digital data between circuits respectively operated by clocks having a first frequency and a second frequency which is different from the first frequency.
2. Description of the Related Art
In order to allow two digital data processing systems having different operating frequencies to exchange digital data, sample rates of digital data must be converted.
U.S. Pat. Application Ser. No. 102,569 assigned by the same assignee of present application discloses an SRC using cascade-connected multistage delay gates for obtaining a phase relationship between two clock signals, which is necessary for linear interpolation of data.
According to the SRC in the first embodiment of the prior application, however, in phase data detection between clocks, if the delay time of the delay gates varies, correct interpolation coefficients cannot be obtained.
Furthermore, in the SRC according to the second embodiment of the prior application, interpolation coefficients are corrected in accordance with a variation in delay time of the delay gates. However, the circuit arrangement of the SRC according to the second embodiment of the prior art becomes complex because of correction of interpolation coefficients.